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SC7315
2-CH OUTPUT STEREO AUDIO PROCESSOR
DESCRIPTION
The SC7315 is a volume, tone (bass and treble), balance (left/ right) and fader processor for quality audio applications in car radio and Hi-Fi systems. Selectable input gain and external loudness function are provided. Control is accomplished by serial I 2C bus microprocessor interface. The AC signal settings is obtained by resistor networks and switches combined with operational amplifiers. Due to the Used CMOS technology, low distortion, low noise and low DC stepping are obtained.
DIP-20-300-2.54
FEATURES
* 2 stereo inputs * Two speaker attenuators: --2 independent speakers control in 1.25dB steps for balance and fader facilities --Independent mute function * All functions programmable via serial I 2C Bus * Loudness function * Volume control in 1.25dB steps * Treble and bass control * Input and output for external equalizer ornoise reduction system Device SC7315 SC7315S
SOP-20-375-1.27
ORDERING INFORMATION
Package DIP-20-300-2.54 SOP-20-375-1.27
BLOCK DIAGRAM
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SC7315
ABSOLUTE MAXIMUM RATING
Characteristics Supply Voltage Operating Temperature Storage Temperature Symbol VS Tamb Tstg Ratings 10.2 -40 ~ +85 -55 ~ +150 Unit V C C
QUICK REFERENCE DATA
Characteristics Supply Voltage Maximum Input Signal Handling Total Harmonic Distortion ,V=1Vrms, f=1kHz Signal to Noise Ratio Channel Separation, f=1kHz Volume Control, 1.25dB Step Bass and Treble Control, 2dB step Fader and Balance Control, 1.25dB step Input Gain, 3.75dB Step Mute Attenuation Symbol Vs VCL THD S/N SC -78.75 -14 -38.75 0 100 Min. 6 2 0.01 106 103 0 +14 0 11.25 0.1 Typ. 9 Max. 10 Unit V Vrms % dB dB dB dB dB dB dB
ELECTRICAL CHARACTERISTICS (Refer to the test circuit)
(Tamb=25C,VS=9.0V,RL=10k Characteristics SUPPLY VOLTAGE
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RG=600 Symbol
all controls flat(G=0), f=1kHz,Unless otherwise specified) Test conditions Min. Typ. Max. Unit
Operating Supply Voltage Operating Supply Current Ripple Rejection of Supply Voltage VOLUME CONTROL Input Resistance Control Range Minimum Attenuation Maximum Attenuation Step Resolution Attenuation Set Error Tracking Error DC Steps SPEAKER ATTENUATORS Control Range
VS IS SVR
6
9 20.0
10.0 35.0
V mA dB
60
80
RIV Crange AV(min)
AV(max) ASTEP
20 70 -1 70 0.5 AV=0 to - 20dB AV=-20 to -60dB -1.25 -3
33 75 0 75 1.25 0
50 80 1 80 1.75 1.25 2 2
k dB dB dB dB dB dB mV mV
EA ET VDC
Adjacent attenuation steps From 0dB to AV max
0 0.5
3 7.5
Crange
35
37.5
40
dB
(To be continued)
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SC7315
(Continued)
Characteristics Step Resolution Attenuation Set Error Output Mute Attenuation DC Steps BASS CONTROL (note 1) Control Range Step Resolution Internal Feedback Resistance TREBLE CONTROL (note 1) Control Range Step Resolution AUDIO OUTPUTS Clipping Level Output Load Resistance Output Load Capacitance Output Resistance DC Voltage Level GENERAL
Symbol SSTEP EA AMUTE VDC
Test conditions
Min. 0.5
Typ. 1.25
Max. 1.75 1.5
Unit dB dB dB
80 Adjacent attenuation steps From 0dB to MUTE 12 1 34 13 1
100 0 1 14 2 44 14 2 3 10 16 3 58 15 3
mV mV
GB BSTEP RB
Maximum boost/cut
dB dB k
Gt TSTEP
Maximum boost/cut
dB dB
VOCL RL CL ROUT VOUT
THD=0.3%
2 4
2.5
Vrms k 10 nF V V 15 V V dB 0.1 0.3 % % % dB 1 2 dB dB
30 4.2
75 4.5
120 4.8
BW=20 ~20kHz,flat output muted Output Noise eNO BW=20 ~20kHz,flat All gains=0dB A curve, all gains =0 dB Signal to Noise Ratio
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2.5 5 3 106 0.01 0.09 0.04 80 103 0 0
S/N d
All gains=0dB; Vo=1Vrms Av=0,VIN=10mV
Distortion
Av=-20dB, VIN=1Vrms Av=-20dB,VIN=0.3Vrms
Channel Separation Left/Right Total Tracking Error BUS INPUTS Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge NOTES:
Sc AV=0 to - dB 20 AV=-20 to -60 dB
VIL VIH IIN Vo Io=1.6mA 3 -5
1
V V A V
+5 0.4
(1) Bass and treble response see Figure 16. The center frequency and quality of the response behavior can be chosen by the external circuitry. A standard first order bass response can realized by a standard feedback network. (2) The input is grounded through the 2.2F capacitor.
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SC7315
PIN CONFIGURATIONS
CREF VDD GND L TREBLE R IN(R) LOUD R NC LOUD L 5 6 7 8 9 16 OUT R 15 BOUT(R) 14 BIN(R) BASS 13 BOUT(L) 12 BIN(L) 11 IN(L) 1 2 3 4 20 SCL 19 SDA 18 DGND 17 OUT L BUS INPUTS
NC 10
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SC7315
TYPICAL CHARACTERISTICS PERFORMANCE
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SC7315
TYPICAL CHARACTERISTICS PERFORMANCE (continued)
Fig.11 Supply Voltage Rejection vs. Frequency
100
Fig.10 Input Separation vs. Frequency
110
Fig.12 Output Clipping Level vs. Supply Voltage
Output Clipping Level (v)
Channel Separation (dB)
Channel Separation (dB)
90
5.0 RL=10k f=1kHz THD=0.3% 4.0
100
80
90
VIN=1Vrms AV=0dB All controls Flat
70 Vsvr=0.5Vrms All Input to GND AV=0dB All controls Flat
3.0
80
60
2.0
70 1.0 1 10 2 10 3 10 4 10 1 10 2 10 3 10 4 10 4 6 8 10 12
Frequency (Hz)
Frequency (Hz)
Supply Voltage (V)
Fig.13 Quiescent current vs. Supply Voltage
9.0
Fig.14 Supply current vs. Temperature
50
Fig.15 Bass resistance vs. Temperature
Quiescent Current (mA)
Quiescent Current (mA)
8.0
8.0 Vs=9V
Bass Resistance (k
30 () 60 90
)
-60 -30 0
8.5
48
46
6.0
7.5
44
4.0
7.0
42
2.0 4 6 8 10 12
6.5
40 -60 -30 0 30 () 60 90
Supply Voltage (V)
Temperature
Temperature
Fig.16 Typical Tone Response (with the Ext components indicated the test circuit)
15
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10
AV=0dB
Tone Response (dB)
5
0
-5
-10
-15 1 10 2 10 3 10 4 10
Frequency (Hz)
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SC7315
APPLICATION NOTES
1. I2C BUS INTERFACE Data transmission from microprocessor to the SC7315 and viceversa takes place through the 2 wires I 2C BUS interface, consisting of the two lines SDA and SCL(pull-up resistors to positive supply voltage must be connected). 2. DATA VALIDITY As shown in Figure 17, the data of the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the dtat line can only change when the clock signal on the SCL line is LOW.
Fig. 17 Data Validity on the I2C BUS
3. START AND STOP CONDITIONS As shown in Figure 18, a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
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Fig. 18 Timing diagram of I2C BUS 4. BYTE FORMAT Every byte transferred on the SDA line must obtain 8 bits. Each byte must be followed by the an acknowledge bit. The MSB is transferred first. 5. ACKNOWLEDGE The master(microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse(see Figure 19). The peripheral(audioprocessor) that acknowledges has to pull-down(LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte , otherwise the SDA line remain at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer.
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SC7315
Fig. 19 Acknowledge on the I2C BUS
6. Transmission without acknowledge Avoiding to detect the acknowledge of the audioprocessor, the microprocessor can use a simpler transmission: simply it waits one clock without checking the slave acknowledgig, and sends the new data. This approach of course is less protected from mis-working and decreases the noise immunity.
SOFTWARE SPECIFICATION
1. Interface protocol The interface protocol comprises:
* * * *
A start conditions A chip address byte, containing the SC7315 address(the 8 th bit of the bytes must be 0). The SC7315 must always acknowledge at the end of each transmitted byte. A sequence of data(N-bytes + acknowledge) A stop condition (P)
SC7315 address MSB LSB MSB DATA LSB ACK MSB DATA LSB ACK P
S 1 0 0 0 0 0 0 0 ACK
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ACK: Acknowledge S: Start P: Stop Max clock speed: 100kbits/sec
Data Transferred (N-Bytes + Acknowledge)
2. Chips address 1 (MSB) 3. Data bytes MSB 0 1 1 0 0 0 0 0 0 1 1 1 B2 0 1 0 1 1 B1 B1 B1 * 0 1 B0 B0 B0 * C3 C3 A2 A2 A2 L C2 C2 A1 A1 A1 * C1 C1 LSB A0 A0 A0 * C0 C0 Volume Control Speaker ATT L Speaker ATT R Loudness control Bass control Treble control Function 0 0 0 0 0 0 0 (LSB)
Note: Ax=1.25dB steps;Bx=10dB steps;Cx=2dB steps;Gx=3.75dB steps;*=no effect.
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SC7315
DETAILED DESCRIPTION OF DATA BYTES
1. Volume MSB 0 0 B2 B1 B0 A2 0 0 0 0 1 1 1 1 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 A2 A1 0 0 1 1 0 0 1 1 A1 LSB A0 0 1 0 1 0 1 0 1 A0 Function Volume 1.25dB steps 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 Volume 10dB steps 0 -10 -20 -30 -40 -50 -60 -70
For example, a volume of -45dB is given by: 00100100 2. Speaker attenuators MSB
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LSB 0 1 B1 B1 B0 B0 A2 A2 0 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 A1 A1 0 0 1 1 0 0 1 1 A0 A0 0 1 0 1 0 1 0 1 Speaker ATT L Speaker ATT R 0
Function
1
0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 0 -10 -20 -30 MUTE
For example, attenuation of 25dB on speaker R is given by: 10110100
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SC7315
3.Loudness function MSB 0 1 0 * * L 0 1 Note:*=no effect 4.Bass and treble MSB 0 0 1 1 1 1 0 1 C3 C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
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LSB * *
Function Loudness control Loudness ON Loudness OFF
LSB C2 C2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C1 C1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 C0 C0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0
Function Bass Terble -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14
1
C3=Sign For Example, bass at - 10dB is obtained by the following 8 bit string is: 01100010.
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SC7315
TEST AND TYPICAL APPLICATION CIRCUIT
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SC7315
PACKAGE OUTLINE
DIP-20-300-2.54 UNIT: mm
2.54
1.27 26.40.3
15 degree
0.51MIN
0.51
SOP-20-375-1.27
UNIT: mm
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10.20.4
7.60.3
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2004.08.03 Page 12 of 13
SC7315
HANDLING MOS DEVICES:
Electrostatic charges can exist in many things. All of our MOS devices are internally protected against electrostatic discharge but they can be damaged if the following precautions are not taken: * Persons at a work bench should be earthed via a wrist strap. * Equipment cases should be earthed. * All tools used during assembly, including soldering tools and solder baths, must be earthed. * MOS devices should be packed for dispatch in antistatic/conductive containers.
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